1. Field of the Invention
The present invention relates to an amplifying circuit, and in particular to an amplifying circuit composed of a basic amplifier and a bias circuit thereof.
In recent years, a MOS semiconductor IC (integrated circuit) technology has remarkably developed, so that the scale of integration and the performance have been improved. This technology is applied to not only a high-performance digital IC but also a high-performance analog IC. For example, an analog-digital hybrid IC by the MOS semiconductor IC technology can realize digital and analog circuits on a single chip by a CMOS process, and is economically advantageous.
In order to apply a CMOS semiconductor IC technology to such a high-performance analog IC, it is important to realize a high-performance analog amplifying circuit using an MOS transistor.
2. Description of the Related Art
FIG. 18 shows an arrangement of a prior art trans-impedance type amplifying circuit 100, which is composed of an inversion amplifying circuit 10 where three-staged basic amplifiers (hereinafter, occasionally abbreviated as amplifiers) 11-13 are connected in cascade, and a feedback resistor RF, hereinafter occasionally indicating the resistance value of the resistor RF, connecting between an input terminal IN and an output terminal OUT of the inversion amplifying circuit 10.
The amplifiers 11-13 are respectively composed of common-source MOS transistors M11, M21, and M31, and load resistors R1, R2, and R3 connected in series to the drains of the MOS transistors M11, M21, and M31.
In the absence of a signal inputted to the input terminal IN, a current does not flow through the feedback resistor RF, so that a bias voltage of the amplifying circuit 100 becomes the same as a bias voltage V0 of the output terminal OUT without any voltage drop being generated at the feedback resistor RF.
It is to be noted that the inversion amplifying circuit 10 shown in FIG. 18 is composed of three basic amplifiers, while an inversion amplifying circuit is generally composed of an odd number of basic amplifiers.
The open loop gain A1 of the amplifier 11 can be expressed by the following equation (1):
A1=gm1*R1xe2x80x83xe2x80x83Eq.(1)
where gm1 is the transconductance of the MOS transistor M11, which can be expressed by the following equation (2):                               g          m1                =                              2            *                          μ              N                        *                          C              OX                        *                                          W                11                                            L                11                                      *                          I              1                                                          Eq        .                  xe2x80x83                ⁢                  (          2          )                    
where xcexcN, COX, W11, L11, and I1 are respectively the electron mobility, the gate metal oxide capacitance, the channel width, the channel length, and the reference current of the MOS transistor M11.
Similarly, the gains A2 and A3 of the amplifiers 12 and 13, and the transconductances gm2 and gm3 of the MOS transistors M21 and M31 can be respectively expressed by the following equations (3)-(6):
A2=gm2*R2xe2x80x83xe2x80x83Eq.(3)
A3=gm3*R3xe2x80x83xe2x80x83Eq.(4)
                              g          m2                =                              2            *                          μ              N                        *                          C              OX                        *                                          W                21                                            L                21                                      *                          I              2                                                          Eq        .                  xe2x80x83                ⁢                  (          5          )                                                  g          m3                =                              2            *                          μ              N                        *                          C              OX                        *                                          W                31                                            L                31                                      *                          I              3                                                          Eq        .                  xe2x80x83                ⁢                  (          6          )                    
where W21, L21, I2, and W31, L31, I3 are respectively the channel widths, the channel lengths, and the reference currents of the MOS transistors M21 and M31.
The open loop gain A of the inversion amplifying circuit 10 can be expressed by the following equation (7):
A=A1*A2*A3xe2x80x83xe2x80x83Eq.(7)
Since the transconductances gm1-gm3 vary depending on a process variable condition and a temperature, and the load resistances R1-R3 also vary independently of the transconductances, the gains A1, A2, and A3 of the amplifiers 11-13 vary extensively.
In case the MOS transistors M21 and M31 and the load resistances R2 and R3 are respectively the same as the MOS transistor M11 and the load resistance R1 for example, the open loop gain A of the inversion amplifying circuit 10 can be expressed by the following equation (8):
A=A13xe2x80x83xe2x80x83Eq.(8)
Accordingly, the open loop gain A of the inversion amplifying circuit 10 in this case varies with the cubic of the variation of the gain A1.
FIG. 19 shows an arrangement of a general preamplifying circuit for an optical receiver using the amplifying circuit 100 shown in FIG. 18. This preamplifying circuit is composed of the amplifying circuit 100, a photo diode PD and an input capacitance CIN connected to the input terminal IN of the amplifying circuit 100. It is to be noted that the input capacitance CIN includes the junction capacitance of the photo diode PD and the input capacitance of the inversion amplifying circuit 10.
In the optical preamplifying circuit, a noise increases when a bandwidth is too wide, while an intersymbol interference caused by a waveform deterioration occurs when the bandwidth is too narrow. Therefore, an allowable range of a cutoff frequency which determines the optimal bandwidth is very narrow. Generally, the optimal range of the cutoff frequency is regarded as 0.6-1.0 times a transmission data rate B.
A close loop bandwidth of the preamplifying circuit will now be obtained. A faint current signal IIN from the photo diode PD inputted from the input terminal IN is divided into the input capacitance CIN and the feedback resistor RF with the values of currents IC and IR Accordingly, circuit equations of the preamplifying circuit are expressed by the following equations (9)-(12):
IIN=IC+IRxe2x80x83xe2x80x83Eq.(9)
VOUTxe2x88x92V0=xe2x88x92A*(VINxe2x88x92V0)xe2x80x83xe2x80x83Eq.(10)
VINxe2x88x92VOUT=RF*IRxe2x80x83xe2x80x83Eq.(11)
                                          V            IN                    -                      V            0                          =                              1                          j              *                              (                                  2                  ⁢                  π                  *                  f                                )                            *                              C                IN                                              *                      I            C                                              Eq        .                  xe2x80x83                ⁢                  (          12          )                    
where f and V0 are respectively a frequency and the above-mentioned bias voltage.
If IC, IR, and VIN are eliminated from Eqs.(9)-(12) to obtain the relationship between an input current IIN and an output voltage VOUT, the following equation (13) is held:                               V          OUT                =                                            -                              A                                  1                  +                  A                  +                                      j                    *                                          (                                              2                        ⁢                        π                        *                        f                                            )                                        *                                          R                      F                                        *                                          C                      IN                                                                                            *                          R              F                        *                          I              IN                                +                      V            0                                              Eq        .                  xe2x80x83                ⁢                  (          13          )                    
In case the open loop gain A of the inversion amplifying circuit 10 greater than  greater than 1, the denominator xe2x80x9c1xe2x80x9d of Eq.(13) can be neglected. Accordingly, a trans-impedance ZT assumes the following equation (14) that is Eq.(13) differentiated by the current IIN. When the frequency f=0, a trans-impedance ZT0 assumes the following equation (15), and a bandwidth f3dB assumes an equation (16) from (|ZT|/ZT0|)2=xc2xd.                               Z          T                =                                            ⅆ                              V                OUT                                                    ⅆ                              I                IN                                              =                                                    -                1                                            1                +                                  j                  *                                                            2                      ⁢                      π                      *                                              R                        F                                            *                                              C                        IN                                                              A                                    *                  f                                                      *                          R              F                                                          Eq        .                  xe2x80x83                ⁢                  (          14          )                    xe2x80x83ZT0=xe2x88x92RFxe2x80x83xe2x80x83Eq.(15)
                              f                                    -              3                        ⁢                          xe2x80x83                        ⁢            dB                          =                  A                      2            ⁢            π            *                          R              F                        *                          C              IN                                                          Eq        .                  xe2x80x83                ⁢                  (          16          )                    
In case the open loop gain A greater than  greater than 1, Eq.(16) indicates that the close loop bandwidth of the preamplifying circuit is determined only by the open loop gain A of the inversion amplifying circuit 10, the input capacitance CIN, and the feedback resistance RF. For the above-mentioned input capacitance CIN and the feedback resistance RF, sufficiently stable values can be designed. However, since the open loop gain A in the amplifier of the MOS transistor extensively varies as mentioned above, it is difficult to confine the bandwidth of the preamplifying circuit into the optimal bandwidth, 0.6-1.0 times a transmission data rate B.
It is accordingly an object of the present invention to provide an amplifying circuit comprising a basic amplifier and a bias circuit thereof, and having a gain A stable against variations of process condition and temperature.
As mentioned above, a variation of gain in the amplifying circuit is caused by a transconductance of a transistor generated on a substrate and a load resistance varied with variations of process condition and temperature. Accordingly, if the basic amplifier and the bias circuit can be composed in the form of canceling a variable electron mobility xcexcN, a gate metal oxide capacitance COX, and the like by the process shown in Eq.(2), the above-mentioned object can be achieved.
As shown in a principle (1) of the present invention in FIG. 1, an amplifying circuit according to the present invention comprises: an amplifier 11 including a drive transistor M11 and a load transistor M12 driven by the drive transistor M11, and a basic bias circuit 21 composed of a series circuit of a drive-side supporting bias transistor M01 having a gate-drain short-circuited, a load-side supporting bias transistor M02 having a gate-drain short-circuited for outputting a bias voltage of the load transistor M12 from a drain, and a reference current source IREF1 for biasing the drive-side and the load-side supporting bias transistors M01 and M02 with a constant current I1 (claim 1).
It is to be noted that while the transistors M11, M12, M01, and M02 in FIG. 1 are an n-channel-type, p-channel type transistors can be similarly applied. Hereinafter, the n-channel transistors will be described unless specified to the contrary. Channel lengths L11, L12, L01, L02, and channel widths W11, W12, W01, and W02 of the transistors M11, M12, M01, and M02 are correspondingly set so that L11=L01, L12=L02, W11=n1*W01, and W12=n1*W02.
When a feedback resistor RF is connected between an input terminal and an output terminal upon such a setting, the gate-source voltage V0 of the transistor M11 becomes almost equal to the gate-source voltage VGS01 of the bias transistor M01. A bias current of the amplifier 11 assumes n1*I1 which is n1 times the constant current I1 of the reference current source IREF1.
Also, the transconductances gm11 and gm21 of the transistors M11 and M21 can be respectively expressed by the following equations (17) and (18):                               g          m11                =                              2            *                          μ              N                        *                          C              OX                        *                                          W                11                                            L                11                                      *                          n              1                        *                          I              1                                                          Eq        .                  xe2x80x83                ⁢                  (          17          )                                                  g          m12                =                              2            *                          μ              N                        *                          C              OX                        *                                          W                12                                            L                12                                      *                          n              1                        *                          I              1                                                          Eq        .                  xe2x80x83                ⁢                  (          18          )                    
Accordingly, the gain A1 of the amplifier 11 can be expressed by the following equation (19):                               A          1                =                                            g              m11                                      g              m12                                =                                                                      W                  11                                *                                  L                  12                                                                              W                  12                                *                                  L                  11                                                                                        Eq        .                  xe2x80x83                ⁢                  (          19          )                    
Namely, the gain A1 becomes irrelevant to xcexcN and COX whose variations are extensive. Furthermore, if the channel length L11 is assumed to be the channel length L12 (accordingly, the channel length L01=the channel length L02, the gain A1 can be expressed by the following equation (20):                               A          1                =                                            W              11                                      W              112                                                          Eq        .                  xe2x80x83                ⁢                  (          20          )                    
According to Eq.(20), the gain A1 can be expressed only by the channel widths W11 and W12 of the transistors M11 and M12.
In case the transistors M11, M12, M01, and M02 are integrated on the same substrate, the above-mentioned conditions of the channel lengths and the channel widths are easily satisfied.
Namely, for the load of the amplifier 11, by using the transconductance gm12 of the load transistor M12 having the same variation factor as the transconductance gm11 of the drive transistor M11, the variation of the transconductance is canceled, thereby realizing a stable amplifying gain A1 independent of the variations of process condition and temperature.
Also, the relationships between the bias transistor M01 and the drive transistor M11, and between the bias transistor M02 and the load transistor M12 are set by the channel length or the channel width, thereby enabling the characteristic of the amplifier to be easily determined. Furthermore, by making the transistors M01, M02, M11, and M12 on the same substrate, the amplifying circuit becomes stable for the temperature variation.
Also, the present invention, as shown in a principle (2) of the present invention in FIG. 2A, may further comprise a load resistor R1 inserted between the drive and the load transistors M11 and M12, and a bias resistor R0 inserted between the drive-side and the load-side supporting bias transistors M01 and M02 (claim 2).
Namely, as shown in FIG. 2B, a transconductance gm increases in proportion to (VGSxe2x88x92VT) in a normal area Z2, while the transconductance gm has a characteristic of being saturated from a certain constant value (see strong inversion area Z3). Accordingly, there is a problem that the transconductance gm12 of the load transistor M12 is saturated and fails to follow Eq.(20) if the channel width ratio W11/W12 of the drive transistor M11 and the load transistor M12 is increased in order to increase the gain.
In order to solve this problem, the load resistor R1 is added. The gain A1 in this case can be expressed by the following equation (21):                               A          1                =                                            g              m11                        *                          (                                                1                                      g                    m12                                                  +                                  R                  1                                            )                                =                                                                      W                  11                                                  W                  12                                                      +                                          g                m11                            *                              R                1                                                                        Eq        .                  xe2x80x83                ⁢                  (          21          )                    
According to Eq.(21), it is possible to improve the gain A1 by the load resistor R1 by using the transconductance gm within the normal area (see FIG. 2B) with the ratio of the channel width being suppressed within a constant range. Namely, although the second term of Eq.(21) is the same as Eq.(1) of the prior art gain A1, it is possible to suppress the gain variation caused by the resistor R1 comparatively small if the gain by the first term is made larger than the gain by the second term, thereby enabling the whole variation of the gain A1 to be suppressed within a range without problems.
Also, the present invention, as shown in FIG. 3, may further comprise a drive-side common-gate transistor M14 inserted between the drive and the load transistors M11 and M12, and a drive-side common-gate bias circuit 22b for providing a bias voltage to a gate of the drive-side common-gate transistor M14 (claim 3).
Generally, a parasitic capacitance between terminals of a transistor must be considered when a high frequency signal is treated. In the drive transistor M11, there is a gate-drain capacitance in addition to a gate-source capacitance (see capacitance CIN in FIG. 19). The gate-drain capacitance looks larger due to the Miller effect when observed from the input side, which causes a decrease of frequency bandwidth.
In order to avoid the Miller effect problem, load impedance of the drive transistor M11 has to be decreased without greatly changing a drain electric potential of the drive transistor M11. Thus, it becomes possible to realize a broad bandwidth by inserting the drive-side common-gate transistor M14 whose input impedance is low between the drive transistor M11 and the load transistor M12 and by decreasing the influence of the Miller effect.
It is to be noted that since the current gain of the common-gate transistor M14=1, the drain current I1 of the drive transistor M11 becomes equal to the drain current of the load transistor M12. Also, the output terminal of the amplifier 11 in this case is the drain terminal of the common-gate transistor M14.
Also, the drive-side common-gate bias circuit 22b may be composed of a bias transistor M05 having a gate-drain short-circuited for outputting the bias voltage from a drain, and a reference current source IREF2 for biasing the bias transistor M05 with a constant current (claim 4).
Also, the present invention, as shown in a principle (4) of the present invention in FIG. 4, may further comprise a load-side common-gate transistor M13 connected between the load transistor M12 and a power supply, and a load-side common-gate bias circuit 22c for providing a bias voltage to a gate of the load-side common-gate transistor M13 (claim 5).
Also, the above-mentioned load-side common-gate bias circuit 22c may be composed of a series circuit of a drive-side supporting bias transistor M05 having a gate-drain short-circuited, a load-side supporting bias transistor M06 having a gate-drain short-circuited for outputting the bias voltage from a drain, and a reference current source IREF2 for biasing the drive-side and the load-side supporting bias transistors M05 and M06 with a constant current (claim 6).
Generally, there is a variation in a power supply voltage varying the drain-source voltage of a load transistor, so that a characteristic of an amplifier varies. The common-gate transistor M13 is inserted in order to decrease the characteristic variation by the power supply voltage variation.
Hereinafter, conditions for generating the bias voltage of the load-side common-gate transistor M13 by the above-mentioned bias circuit 22c will be described. The square law of Eq.(22) is held between the drain current I1 and a gate-source voltage VGS of the transistor M02. From Eq.(22), the following equation (23) can be led:                               I          D                =                                                            μ                N                            *                              C                OX                                      2                    *                      W            L                    *                                    (                                                V                  GS                                -                                  V                  T                                            )                        2                                              Eq        .                  xe2x80x83                ⁢                  (          22          )                                                              V            GS                    -                      V            T                          =                                            2                                                μ                  N                                *                                  C                  OX                                                      *                          L              W                        *                          I              D                                                          Eq        .                  xe2x80x83                ⁢                  (          23          )                    
Also, in order that the transistor M02 operates in the saturated area, the following equation (24) has to be held:                                           V            DS                    ≥                                    V              GS                        -                          V              T                                      =                                            2                                                μ                  N                                *                                  C                  OX                                                      *                          L              W                        *                          I              D                                                          Eq        .                  xe2x80x83                ⁢                  (          24          )                    
If the gate-source voltages of the transistors M01, M02, M03, M05, and M06 are respectively assumed to be VGS01, VGS02, VGS03, VGS05, and VGS06, the following equation (25) is held:
VDS02=(VGS05+VGS06)xe2x88x92VGS03xe2x88x92VGS01xe2x80x83xe2x80x83Eq.(25)
In case VGS05=VGS01, the following equation (26) is held:                                                                         V                DS02                            =                              xe2x80x83                            ⁢                                                V                  GS06                                -                                  V                  GS03                                                                                                        =                              xe2x80x83                            ⁢                                                                                          2                                                                        μ                          N                                                *                                                  C                          OX                                                                                      *                                                                  L                        06                                                                    W                        06                                                              *                                          I                      1                                                                      -                                                                                                        xe2x80x83                            ⁢                                                                    2                                                                  μ                        N                                            *                                              C                        OX                                                                              *                                                            L                      03                                                              W                      03                                                        *                                      I                    1                                                                                                                          ≥                              xe2x80x83                            ⁢                                                                    2                                                                  μ                        N                                            *                                              C                        OX                                                                              *                                                            L                      02                                                              W                      02                                                        *                                      I                    1                                                                                                          Eq        .                  xe2x80x83                ⁢                  (          26          )                    
From Eq.(26), the following equation (27) can be led:                                                         L              06                                      W              06                                      ≥                                                            L                02                                            W                02                                              +                                                    L                03                                            W                03                                                                        Eq        .                  xe2x80x83                ⁢                  (          27          )                    
In case the relationships between the channel lengths and the channel widths of the transistors M02 and M03 are such that the channel length L03=the channel length L02 and the channel width W03=the channel width W02, the following equation (28) is held:                                           L            06                                W            06                          ≥                  4          *                                    L              02                                      W              02                                                          Eq        .                  xe2x80x83                ⁢                  (          28          )                    
Namely, in order that the bias circuit 22 of the load-side common-gate transistor M13 generates such a bias voltage that the load transistor M12 operates in the saturated area, it should be rendered that a channel width W05=the channel width W01, and the channel width W06=the channel width W02/4 when the sizes of e.g. the transistors M12 and M13 are equal. Thus, it becomes possible to decrease the influence of the power supply voltage variation and to realize a more stable gain characteristic.
Also, the basic bias circuit 21c may have a common-gate supporting bias transistor M03 inserted between the load-side supporting bias transistor M02 and the reference current source IREF1 within its own circuit, and which inputs the bias voltage of the load-side common-gate bias circuit 22 to a gate (claim 7).
Also, the common-gate transistors M13 and M03 of the basic amplifier 11c and the basic bias circuit 21c may respectively have threshold voltages for performing a saturated area operation with a gate-source voltage equal to or less than threshold voltages of the load transistor M12 and the load-side supporting bias transistor M02 (claim 8).
Thus, by using the common-gate transistor M13 and the common-gate supporting bias transistor M03 whose threshold voltages are low, it becomes possible to make the bias voltages of the bias circuits 21c and 22c in FIG. 4 the same, as shown in a principle (5) of the present invention in FIGS. 5A and 5B, to share the bias voltage of the bias circuit 21d among the transistors M12 and M13, and to omit the bias circuit 22c. 
Namely, the basic bias circuit 21d may be used for the load-side common-gate bias circuit 22c (claim 9).
From FIG. 5A, it is found that the condition of the saturated operation in the transistor M02 is given by the following equation (29). From Eq.(29), the equation (30) can be led, where VDS02, VGS02, VT02, VGS03 are respectively the drain-source voltage, the gate-source voltage, and the threshold voltage of the transistor M02, and the gate-source voltage of the transistor M03.
VDS02=VGS02xe2x88x92VGS03xe2x89xa7VGS02xe2x88x92VT02xe2x80x83xe2x80x83Eq.(29)
VT02xe2x89xa7VGS03xe2x80x83xe2x80x83Eq.(30)
FIG. 5B shows a relationship between the threshold voltage VT03 of the above-mentioned common-gate transistor M03 and the threshold voltage VT02 of the load-side supporting bias transistor M02.
When an enhancement-mode transistor M02 operates with a drain current ID=I1 in the saturated area, the gate-drain voltage VGS02 and the threshold voltage VT02 have a mutual relationship shown in FIG. 5B. From the above Eq.(30), the gate-source voltage VGS03 of the transistor M03 has to be on the left side where the gate-source voltage VGS03 is smaller than the threshold voltage VT02.
In case the threshold voltage VT03 of the transistor M03 is negative, that is a depletion-mode transistor, the drain current=I1 can be flowed with the gate-source voltage being VGS03.
When the gate-source voltage VGS is assumed to be the same as the threshold voltage VT02, a transistor MXX having a characteristic shown by a dashed line can also flow the drain current=I1. Since the threshold voltage VTXX of the transistor MXX is positive, the transistor MXX is the enhancement-mode transistor. However, it has a lower threshold voltage than the transistor M02.
Similarly, in case the transistor M02 is the depletion-mode transistor, the threshold voltage of the depletion-mode transistor M03 can be determined.
Also, in the present invention, as shown in a principle (6) of the present invention in FIG. 6B, a substrate (bulk) and a source of the load transistor M12 and the load-side supporting bias transistor M02 may be short-circuited (claim 10).
FIGS. 6A-6D show a principle (6) of the present invention, in which FIG. 6A is the same as FIG. 1. Although being not shown in FIG. 6A, bulk terminals of the n-channel transistors M11, M12, M01, and M02 are connected to a node T whose potential is the lowest. Also, the bulk terminals of the p-channel transistors are connected to a node (not shown) whose potential is the highest.
In these cases, occasionally the potential of the source terminal is different from that of the bulk terminal. As mentioned above, the relationship between the drain current ID and the gate-source voltage VGS in the saturated area of the MOS transistor has been expressed by Eq.(22).
However, since the channel through which the drain current ID flows is an area sandwiched between the gate and the bulk, the drain current ID is influenced not only by the gate-source potential difference VGS but also by a source-bulk potential difference VSB.
Namely, even if the potential difference VGS does not change, a threshold voltage VT related to a channel formation changes as the potential difference VSB changes. The threshold voltage VT in consideration of the potential difference VSB can be expressed by the following equation (31):
VT=VT0+xcex3({square root over (2"PHgr"f+VSB)}xe2x88x92{square root over (2"PHgr"f)})xe2x80x83xe2x80x83Eq.(31)
where VT0 is the threshold voltage VT when VSB=0, xcex3 is a constant determined depending on a process, and xcfx86f indicates a fermi level.
Eq.(31) indicates a substrate bias effect in which the threshold voltage VT changes as the VSB changes.
FIG. 6C shows an influence of the substrate bias effect in FIG. 6A. The dot-dash line in FIG. 6C indicates the source voltage (VBxe2x88x92VGS12) of the transistor M12 when the connection between the source and the bulk of the transistor M12 is short-circuited (VSB=0), while the solid line indicates the source voltage (VBxe2x88x92VGS12) in case the bulk terminal of the transistor M12 is connected to the node T (source of the transistor M11, see FIG. 6A) whose potential is the lowest.
It is seen from FIG. 6C that VGS12 increases as the threshold voltage VT of the load transistor M12 increases due to the substrate bias effect, a possibility of shortage of the power supply voltage arises, and that the gain A1 (gradient of the solid line) decreases.
The solid line in FIG. 6D is the same as the dot-dash line in FIG. 6C. It is found that by the short-circuit between the source and the bulk of the transistor M12, the shortage of the power supply voltage caused by the substrate bias effect does not occur and the gain A1 does not decrease.
Also, in the present invention, an amplifying circuit may comprise 2Nxe2x88x921 basic amplifiers, where N is a natural number, connected in cascade, a feedback resistor connected between an input terminal of a first stage of the basic amplifiers and an output terminal of a last stage of the basic amplifiers, and the basic bias circuit (claim 11).
Namely, an odd number of basic amplifiers are connected in cascade to compose an inversion amplifying circuit, and a negative feedback is effected to the inversion amplifying circuit by the feedback resistor, thereby enabling an amplifying circuit for supplying a bias voltage by the basic bias circuit to be composed. Thus, the amplifying circuit having a stable gain and a cutoff frequency can be realized.
Also, an optical device may be connected to the input terminal of the amplifying circuit (claim 12). Namely, it is possible to amplify a current signal inputted from the optical device.
Also, the basic bias circuit may be commonly used for the basic amplifiers (claim 13). Thus, it becomes possible to decrease the number of the basic bias circuits.
Also, the present invention may further comprise an input bias circuit composed of a series circuit of a drive-side supporting transistor having a gate-drain short-circuited for outputting a bias voltage, from a drain, provided to a gate of the drive transistor M11, and a load-side supporting transistor whose gate is connected to a bias voltage of the basic bias circuit 21 (claim 14).
Thus, an input operation point of the drive transistor M11 is determined by the input bias circuit, and the amplifier 11 can be used as an amplifying circuit of an open loop.
Furthermore, in the present invention, the drive and the load transistors may be integrated on a same substrate with only a channel width being different (claim 15).